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[Other resource] 一篇用VHDL实现快速傅立叶变换的论文

Description: 一篇用VHDL实现快速傅立叶变换的论文，包括原理分析和代码实现，印度圣雄甘地大学M.A.学院提供-VHDL with a Fast Fourier Transform papers, including the principle of analysis and implementation of the code, the Mahatma Gandhi Institute of the University of Marat
Platform: | Size: 63132 | Author: 咱航 | Hits:

[VHDL-FPGA-Verilog] 一篇用VHDL实现快速傅立叶变换的论文

Description: 一篇用VHDL实现快速傅立叶变换的论文，包括原理分析和代码实现，印度圣雄甘地大学M.A.学院提供-VHDL with a Fast Fourier Transform papers, including the principle of analysis and implementation of the code, the Mahatma Gandhi Institute of the University of Marat
Platform: | Size: 62464 | Author: | Hits:

[VHDL-FPGA-Verilog] pseudorandom

Description: 伪随机m序列产生的VHDL语言程序- program in VHDL language for generating pseudo-random m sequence
Platform: | Size: 2048 | Author: 张庆辉 | Hits:

[Communication] 伪随机序列

Description: 线形反馈移位寄存器（LFSR)是数字系统中一个重要的结构，本程序可以自动产生AHDL,VHDL,Verilog的源代码及电路原理图。程序可以运行在win98/2000/NT平台-linear feedback shift register (LFSR) digital system is an important structure, the process can be automatically generated AHDL, VHDL, Verilog source code and circuit schematics. Procedures can run on platforms win98/2000/NT
Platform: | Size: 162816 | Author: 夏沫 | Hits:

[Program doc] m序列发生器

Description: m序列发生器(简单型码序列发生器-----simple shift register generator)-m sequence generator (a simple code sequence generator----- simple shift Regi ster generator)
Platform: | Size: 3072 | Author: | Hits:

[VHDL-FPGA-Verilog] mxuliematlab

Description: m序列在dspbuilder下产生VHDL源码及其测试激励文件的matlab模型,在modelsim下仿真通过-m sequence in dspbuilder under VHDL source code and test incentives document matl ab model, the simulation under through modelsim
Platform: | Size: 5120 | Author: zqh | Hits:

[Internet-Network] eathnet

Description: 百兆以太网mac和mii的vhdl源程，作IPcore的时候非常有用-Fast Ethernet MII and the VHDL source way for IPcore very useful when
Platform: | Size: 123904 | Author: 王前 | Hits:

[VHDL-FPGA-Verilog] EthernetMAC10100Mbps.tar

Description: ethernet 10 0M MAC-ethernet MAC 10,100 M
Platform: | Size: 934912 | Author: wing | Hits:

[VHDL-FPGA-Verilog] DCT_vhdl

Description: IDCT-M is a medium speed 1D IDCT core -- it can accept a continous stream of 12-bit input words at a rate of -- 1 bit/ck cycle, operating at 50MHz speed, it can process MP@ML MPEG video -- the core is 100％ synthesizable-IDCT-M is a medium speed 1D IDCT core-- it ca n accept a continuous stream of 12-bit input word 's at a rate of-- 1 bit/ck cycle, operating at 50MHz speed, it can process MP @ ML MPEG video-- the core is 100 % synthesizable
Platform: | Size: 10240 | Author: 陈朋 | Hits:

[Communication-Mobile] turbo_VHDL

Description: Turbo Decoder Release 0.3 * Double binary, DVB-RCS code * Soft Output Viterbi Algorithm * MyHDL cycle/bit accurate model * Synthesizable VHDL model -Turbo Decoder Release 0.3* Double binary, DVB-RCS code* Soft Output Viterbi Algorithm* M yHDL cycle/bit accurate model* Synthesizable VHDL model
Platform: | Size: 154624 | Author: | Hits:

[Other] m_cov_cul03_unmodule_precise

Description: 该程序用以对m序列码的调制在负dB情况下解调的仿真，是对基带信号的调制-procedures for the right sequence code m in the negative dB modulation of the demodulation simulation of the base band signal modulation
Platform: | Size: 1024 | Author: 孙晓东 | Hits:

[VHDL-FPGA-Verilog] V+m511

Description: M序列编码-M coding sequence
Platform: | Size: 66560 | Author: sss | Hits:

[Other] MP3_VHDL

Description: MP3的VHDL源码，用硬件语言实现的MP3，不错的资料-MP3 of the VHDL source code, using hardware language to achieve MP3, good information
Platform: | Size: 36864 | Author: 沈三思 | Hits:

[VHDL-FPGA-Verilog] vhdl

Description: 伪随机序列发生器的vhdl算法 设计一个伪随机序列发生器，采用的生成多项式为1+X^3+X^7。要求具有一个RESET端和两个控制端来调整寄存器初值（程序中设定好四种非零初值可选）。 -Pseudo-random sequence generator algorithm VHDL design of a pseudo-random sequence generator, using the generation polynomial for the 1+ X ^ 3+ X ^ 7. RESET has a client request and the two control registers client to adjust the initial value (procedures set of four non-zero initial value optional).
Platform: | Size: 1024 | Author: 文成 | Hits:

[MiddleWare] M_generate

Description: m序列产生编码，vhdl硬件实现用于实现调制解调-m sequence code generated, vhdl hardware implementation for the realization of modulation and demodulation
Platform: | Size: 247808 | Author: xiaohuaifeng | Hits:

[VHDL-FPGA-Verilog] CPLD_raoma

Description: 基于CPLD的扰码与解扰码器的设计，扰码用M序列实现，m序列级数和频率可选-CPLD based on the scrambling code and Descrambling codec design, scrambling code sequence with M realize, m sequence of series and frequency optional
Platform: | Size: 39936 | Author: 梁奔山 | Hits:

[VHDL-FPGA-Verilog] m

Description: 扩频接收机设计的部分，一个用vhdl语言编写的m序列生成器，-A language with vhdl generator sequence m
Platform: | Size: 107520 | Author: 程乐 | Hits:

[VHDL-FPGA-Verilog] 2mxulie

Description: 基于CPLD的数字通信系统 2m序列 用VHDL产生 2m序列信号-CPLD-based digital communications systems using VHDL generate 2m sequence signal sequence 2m
Platform: | Size: 3072 | Author: 石一鸣 | Hits:

[VHDL-FPGA-Verilog] M-sequence-generator

Description: M sequence generator using VHDL-M sequence generator
Platform: | Size: 211968 | Author: jkl | Hits:

[Program doc] m

Description: m序列信号发生器的设计，用于保密通信，和信息加密，属于流密码。-m sequence signal generator designed for confidential communications, and information encryption, part of stream ciphers.
Platform: | Size: 151552 | Author: yuhai | Hits:
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